The present invention related generally to MOSFET devices, and specifically to a novel floating well vertical MOSFET device implementing a gate control means for use in Dynamic Random Access Memory (DRAM) cell applications.
The key challenge in scaling of MOSFET is to improve the drive current and to keep sufficiently low off-state leakage current. As the gate oxide and channel length are scaled down, the operating voltage has also been scaled down continuously. The threshold voltage can not be scaled down as aggressively as the operating voltage because of the subthreshold leakage. Therefore, the gate over-drive is reduced while keeping low leakage in off-state. One possible solution is the dynamic threshold voltage MOSFET (DT-MOSFET) which connects the gate to a well. In the DT-MOSFET, high drive current and low off current can be obtained because of low threshold voltage in on-state and high threshold voltage in off-state. Unfortunately, the leakage current of the forward biased pn-junction at the source fatally increases at supply voltage higher than 0.7V. Therefore, the supply voltage must be reduced to be below 0.7V. In DRAM application, off-state leakage current, which limit the retention time, is very critical. Negative word line voltage has been proposed to reduce the off-state subthreshold leakage while keeping enough gate over-drive especially at write back conditions when the source of the transistor is near bit line high voltage level. With the negative word line low approach, another voltage source is needed and the device is more prone to gate induced drain leakage (GIDL) current.
It would thus be highly desirable to provide a floating well vertical MOSFET device implementing a gate control means to enable greater gate over-drive and drive currents.